In order to make integrated circuits (ICs) such as memory, logic and other devices, of higher integration density than currently feasible, one has to find a means to further scale down the FET devices that are present therein. Moreover, as FET dimensions are scaled down, it becomes increasingly difficult to control short-channel effects by conventional means. Short-channel effects, as well known to those skilled in the art, are the decrease in threshold voltage, Vt, in short-channel devices, i.e., sub-0.1 micron, due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
An evolution beyond the standard single gate metal oxide semiconductor field effect transistor (MOSFET) is the double-gate MOSFET, where the device channel is confined between top and bottom gate dielectric layers. This structure, with a symmetrical gate structure, can be scaled to about half of the channel length as compared to a conventional single gate MOSFET structure. It is well known that a dual gate or double-gate MOSFET device has several advantages over conventional single gate MOSFET devices. Specifically, the advantages for dual gate MOSFET devices over their single gate counterparts include: a higher transconductance, lower parasitic capacitance, and improved short-channel effects. For instance, Monte-Carlo simulation has been previously carried out on a 30 nm channel dual gate MOSFET device and has shown that the dual gate device has a very high transconductance (2300 mS/mm) and fast switching speeds (1.1 ps for nMOSFET).
Moreover, improved short-channel characteristics are obtained down to 20 nm channel length with no doping needed in the channel region. This circumvents the tunneling breakdown, dopant quantization, and dopant depletion problems associated with channel doping that are normally present with single gate MOSFET devices.
Some examples of prior art double-gate MOSFETs are found in the following references:
U.S. Pat. No. 5,188,973 describes a double-gate structure in which the bottom gate is not self-aligned to the top gate. This prior art double-gate structure is quite different from the inventive double-gate structure described herein because the inventive DGFET includes self-aligned isolation oxide regions that are formed while the Si channel region is encapsulated with nitride. No such self-aligned oxide isolation regions and encapslation is disclosed in the '973 patent.
U.S. Pat. Nos. 5,140,391 and 5,349,228 describe other types of double-gate structures. In these prior art double-gate structures, the Si channel region is not encapsulated with nitride during formation of oxide isolation regions. Moreover, these prior art structures do not include self-aligned oxide isolation regions.
To date, prior art methods for fabricating double-gate MOSFETs have either been very complex or have severe drawbacks in terms of parameter control. Moreover, some of the structures known in the art have large parasitic capacitance between the back-gate and the source/drain regions. This can be reduced by increasing the back-gate dielectric thickness, but with the penalty of reduction of back-gate control, and poorer scaling properties. When low capacitance is desired, the back-gate dielectric should be approximately 20× thicker than the front gate dielectric, but when greater effective control is desired, the back-gate dielectric should be approximately 2–4× thicker than the front gate.
Co-assigned U.S. Pat. No. 5,773,331 describes a structure and method for fabricating a double-gate MOSFET structure in which the above problems have been solved. In particular, the '331 patent describes a double-gate MOSFET having sidewall source and drain contacts and bottom and top gate oxides that are self-aligned. The structure disclosed in the '331 patent has low parasitic capacitance to the bottom gate and a reduced drain and source resistance as compared to other prior art double-gate MOSFETs.
In the '331 patent, the double-gate MOSFET having the above-mentioned characteristics is obtained by the steps of: forming a channel layer; forming a top gate insulator layer on the channel layer; forming a top gate on the top gate insulator; forming a gate pillar on the top gate; forming insulating sidewall layers adjacent to the top gate and the gate pillar; forming an integral source/drain region within the channel layer by introduction of dopants; forming conductive amorphous sidewalls on either side of, and adjacent to the insulating sidewall layers, one of the amorphous silicon sidewalls being connected to the drain region and the other being connected to the source region; and etching the channel layer using the top gate, gate pillar, insulating sidewall layers and amorphous silicon sidewalls as a mask, thereby transferring the lateral extension of the mask into the channel layer, providing for a channel with integral source/drain regions being raised with respect to the support structure.
Despite being capable of providing self-aligned top and bottom gates, the prior art double-gate MOSFET disclosed in the '331 patent does not provide self-aligned oxide isolation regions and complete nitride encapsulation of the Si channel region. As such, the '331 patent does not provide a DGFET which has its lowest possible parasitic capacitance.